Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Design of very large scale integration (VLSI) circuits can be an error prone, time consuming, and tedious task. To facilitate design of three-dimensional (3D) integrated circuits, pre-designed sub-circuits or modules may be used. In block level circuit design, placement of the modules takes into consideration performance factors, such as electrical hazards (or crosstalk), creation of heat, and delays in propagating signals, for example. To minimize such operational risks, modules may be placed at safe distances from each other that may vary due to the desired performance factor. At the same time, modules may be placed in close proximity so that an overall amount of space required realizing the VLSI circuitry is optimized. Blocks may also be placed in close proximity to minimize wiring required to connect blocks.
A demand of decreasing feature size (e.g., from micro to nanometers) and increasing chip dimension (e.g., incorporating millions of transistors) has resulted in changes of technology from 2D to 3D, and challenges in designing VLSI circuits have increased due to increased interconnect delays and high power budgets in designs, for example. Challenges are multidimensional, ranging from factors such as area or space minimization and layers of interconnect minimization in 3D design to several performance requirements such as signal interference involving 3D parasitics, signal propagation delays, and thermal hazards, for example.